The present invention relates to programmable logic arrays and more particularly to a timing circuit for a non-overlapping, two-phase-clocked programmable logic array implemented with complementary insulated-gate field-effect transistor technology.
A programmable logic array (PLA) provides a regular structure for implementing combinatorial and sequential logic functions. For example, the PLA can be programmed such that a series of inputs can be arranged into sum-of-products expressions, with each output from the PLA corresponding to a different expression. A typical PLA employs a structure including an AND plane, an OR plane, and an AND/OR plane connected therebetween.
The AND plane includes M rows and N columns. Each column corresponds to an input signal and has a pair of column conductor. The first column conductor carries the non-inverted input signal, and the second column conductor carries the inverted input signal. Each row has a pair of transistors and a pair of row conductors. The first row transistor, a p-channel type, forms a controlled current path between the first row conductor and a source of operating potential, thereby serving a "precharge" function; the second transistor, an n-channel type, forms a controlled current path between the second row conductor and a reference potential, thereby serving an "evaluate" function. The gates of the two row transistors are tied together.
The OR plane includes M rows and P columns, wherein each row contains a corresponding row conductor from the AND plane. Each column consists of two column transistors and two column conductors. The first column transistor, a p-channel type, forms a controlled current path between the first column conductor and a source of operating potential, thereby serving a "precharge" function. The second transistor, a n-channel type, forms a controlled current path between the second column conductor and a reference potential, thereby serving an evaluate function. The gates of the two column transistors are tied together. The first column conductors carry the output signals from the OR plane.
The AND/OR plane connects the rows of the AND plane to the rows of the OR plane. For each row, this function is typically implemented by a pair of series-connected inverters which provide for level refreshment of the signal generated by the AND plane.
Realization of a sum of products is achieved by interconnecting the rows and columns of each plane. This "programming" is implemented with n-channel transistors. Products (minterms) are evaluated in the AND plane; each term of the product is realized by connecting the source-drain path of the n-channel transistor between the corresponding first and second row conductors of a given row, and connecting the gate to the appropriate column conductor. The choice of column conductors depends upon whether the inverted (complementary) or non-inverted input signal is desired. The summation of the products is realized in the OR plane where an n-channel transistor connects the first row conductors (each representing a product of terms) with the first column conductor. By connecting the source-drain path of the n-channel transistor between the first and second column conductors of a given column and the gate to the first conductor from a given row, the product from that given row is added to the output for the given column. Thus, the number of n-channel transistors and their respective positions in the AND and OR planes are determined by the desired combinational logic function.
The typical CMOS PLA employs a 2-phase, non-overlap clocking strategy. The first clock phase is used to latch the input signals to the AND plane; the second clock phase is used to transmit output signals from the OR plane.
In addition to the two clock phases, internal timing must be employed in order to allow adequate time for the signals on the row conductors to propagate from the AND plane to the OR plane. This propagation time is referred to as "evaluation" time. Each n-channel transistor exhibits a capacitance that is a function of the area of the source and drain regions. Thus, each n-channel transistor connected to a first row conductor adds a capacitance thereto which delays the propagation time of a signal into the OR plane. If an input signal of every column is used to form a product, there will be one transistor in each column of a given row. In this instance, the longest evaluation time will result when only one row transistor reverses the charge of the line capacitance in response to the input signal. Therefore, the PLA must provide a subcircuit for allowing adequate time for the evaluation of the minterms.
The typical timing circuit of a CMOS PLA employs a dummy row in the AND and AND/OR planes. The dummy row has p-channel and n-channel transistors whose gates are driven by the first clock phase, and two conductors. The source-drain path of the p-channel transistor is connected between a source of operating potential and the first dummy row conductor; the source-drain path of the n-channel transistor is connected between the second dummy row conductor and a reference potential. A pair of n-channel transistors corresponding to each column have their drain-source paths connected between the two dummy row conductors. The gate of one n-channel transistor is coupled to the first column conductor, and the gate of the other n-channel transistor is coupled to the second column conductor.
The AND/OR plane employs a Schmitt trigger having its input coupled to the first dummy row conductor. The output of the Schmitt trigger drives the gates of each pair of column transistors in the OR plane. Thus, by the time the Schmitt trigger snaps on, the minterms on the row conductors have been evaluated.
For a general discussion of programmable logic arrays, see a book entitled "Principles of CMOS VLSI Design" by Neil Weste and Hamran Eshraghian, published by Addison-Wessley Publishing Company, 1985, pp. 368-73. In particular, chapter 8.7.4 describes a typical PLA implemented with CMOS technology using a strict 2-phase clocking strategy. This PLA incorporates transistors in the dummy row and a Schmitt trigger in the AND/OR plane.
Problems in the typical PLA arise from the use of transistors in the dummy row. Because two transistors are employed for each input signal, the load capacitance of that row is twice as great as that for the actual worst-case evaluation time scenario. Clearly, this additional capacitance slows the performance time of the PLA. Furthermore, half the transistors in the dummy row are constantly "on" which consumes power. Other problems in the dummy row relate to the manufacturing process. The CMOS PLAs are made as integrated circuits and therefore exhibit variations in delay due to manufacturing imperfections. Additionally, these transistors take up space on the chip and add to the cost of the circuit.
The Schmitt trigger also provides a source of problems. In addition to the added capacitance of the dummy row, the internal capacitance and hysteresis of the Schmitt trigger adds to the delay of the PLA. Furthermore, the performance of the Schmitt trigger does not preclude malfunctions.
Therefore, it is an object of the present invention to provide a CMOS programmable logic array with a new and improved dummy row.